A successive approximation ADC produces an n-bit digital output by comparing a sampled and held analog input signal with the output of an internal digital-to-analog converter (DAC), using a successive approximation logic and registers controlled in such a way that the DAC output value converges towards the held input value. This is typically accomplished by splitting the voltage range in half in consecutive clock cycles to determine where the input signal lies. Thus, an eight-bit successive approximation ADC, for example, converges to a final result by taking eight consecutive "guesses," or successive approximations. An example of such ADC is described in U.S. Pat. No. 4,679,028, incorporated herein by reference.
One approach to successive approximation ADCs is the charge redistribution, weighted capacitor array ADC, an example of which is described in James L. McCreary and Paul R. Gray, "All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques," IEEE Journal of Solid State Circuits, Vol. SC-10, No. 6, December 1975, at pages 371-379 and U.S. Pat. No. 4,399,426, both incorporated herein by reference. In this approach, a plurality of capacitors are used as the precision elements of a charge redistribution array and given binary weighted values. The capacitors are charged by the analog input signal, then sequentially switched for successive comparisons of the stored input signal with corresponding successive divisions (halvings) of an applied reference signal. The sequence of comparator outputs from the comparison steps provides the sequence of digital output bits, most to least significant bit, of the digital word representation of the analog input.
FIG. 1 shows a charge redistribution analog-to-digital converter (ADC) 10 in accordance with the prior art. ADC 10 has a capacitor array 12 interconnected via conductor 14 to a comparator 16. The output 18 of comparator 16 is connected to control, sequence and storage circuit 20 which produces the digital data bits output on DATA OUT lines 22a through 22e. Circuit 20 is comprised of successive approximation logic circuits which activate, control and sequence switches (such as MOS transistor switches) via conductors 24a through 24n to capacitor array 12.
As shown in FIG. 2, capacitor array 12 is comprised of a plurality of capacitors 26-36, connected in parallel. Capacitors 26-34 are binary weighted so that capacitor 26 corresponding to the most significant bit (MSB) has the largest value (16C), capacitor 28 corresponding to the next bit has a value (8C) which is one-half the value of capacitor 26, capacitor 30 corresponding to the next bit has a value (4C) which is one-half the value of capacitor 28, capacitor 32 corresponding to the next bit has a value (2C) which is one-half the value of capacitor 30, and capacitor 34 which corresponds to the least significant bit (LSB) has a value (C) which is one-half the value of capacitor 32. There is one additional capacitor 36 having the same value (C) as the value of the least significant bit capacitor 34.
Capacitors 26-36 have their top plates commonly connected to line 42 to one input (the non-inverted input) of voltage comparator 16 and to a switch S1 which, when connected to point A, is open and, when connected to point B, is closed to connect the top plates to ground. The bottom plates of capacitors 26-36 are connected to switches S2-S7, respectively, which may alternately be connected to point A which is connected to ground or to point B which is connected to switch S8. Switch S8 may be alternately connected to point A which is connected to an input terminal for receipt of voltage V.sub.IN to be digitized, or to point B which is connected to a reference voltage terminal for receipt of a reference voltage V.sub.REF.
Analog-to-digital conversion is accomplished by three operations: sample, hold and redistribution. In sample mode, switches S1-S7 are set to points B, and switch S8 is set to point A. This grounds the top plates of capacitors 26-36 and charges their bottom plates to potentials proportional to the analog input V.sub.IN. In hold mode, switches S1-S7 are set to points A, which disconnects line 14 from ground and connects the bottom plates of capacitors 26-36 to ground. Since the voltage cannot change instantaneously across capacitors 26-36, the potential at analog summing node 42 goes to -V.sub.IN. Finally, in redistribution mode, the successive approximation technique is utilized to determine the data bits for the digital conversion.
Successive approximation begins by testing the value of the most significant bit (MSB). Switches S2 and S8 are set to points B, connecting V.sub.REF to the bottom plate of capacitor 26. Switch S1 remains in its A position. The remaining switches S3-S7 remain set to points A. This establishes a voltage divider circuit between two equal capacitances, capacitor 26 (16C) connected between V.sub.REF and node 42, and capacitors 28-36 (8C+4C+2C+C+C=16C) connected between node 42 and ground. The voltage V.sub.X (at summing node 42 which inputs to comparator 16), which was equal to -V.sub.IN previously, is now increased by one-half the reference voltage V.sub.REF to V.sub.X =-V.sub.IN +V.sub.REF /2. Comparator 16 senses the polarity of V.sub.X and outputs a logic "1" if V.sub.X &lt;0 and a logic "0" if V.sub.X &gt;0. This determines the value of the most significant or 4th bit "b4". Thus, MSB=1 if V.sub.IN &gt;V.sub.REF /2 and MSB=0 if V.sub.IN &lt;V.sub.REF /2. The output on conductor 18 (FIG. 1) is the value of the binary bit being tested. Switch S2 is returned to point A (ground) if the MSB=0, or left at point B (V.sub.REF) if the MSB=1.
In a similar manner, the next MSB is determined by setting switch S3 to point B to connect the bottom plate of the next largest capacitor (viz. capacitor 28) to V.sub.REF, and checking the polarity of the resulting value of V.sub.X produced at node 42. Here, the voltage division property of capacitor array 12 causes V.sub.REF /4 to be added to V.sub.X : EQU V.sub.X =-V.sub.IN +(b4.times.V.sub.REF /2)+V.sub.REF /4.
Comparator 16 will again output a logic 1 if V.sub.X &lt;0 and a logic 0 if V.sub.X &gt;0. This determines the value of the next most significant or 3rd bit "b3". Thus, b3=1 if V.sub.IN &gt;(b4.times.V.sub.REF /2)+V.sub.REF /4 and b3=0 if V.sub.IN &lt;(b4.times.V.sub.REF /2)+V.sub.REF /4. The output on conductor 18 (FIG. 1) gives the value of the next MSB binary bit being tested. Switch S3 is returned to point A (ground) if b3=0, or left at point B (V.sub.REF) if b3=1.
Conversion proceeds in this manner until all bits in the digital representation have been determined. The final configuration of the capacitor array 12 will have those switches S2-S6 that correspond to bits of logic 0 set to point A, and those that correspond to bits of logic 1 left at point B. Thus, n redistributions are required for a conversion resolution of n bits. The logic outputs from comparator 16 serve as inputs to activate, control and sequence the positionings of switches S1-S8.
In the prior art, the most common method utilized for diagnostic testing of successive approximation ADCs is off-line testing. A known analog voltage input signal V.sub.IN is injected at the ADC input and converted to a digital value. The observed actual digital output word resulting from the conversion is then compared with the expected known correct digital result. If the actual digital output differs from the correct digital output, the components are trimmed, and the process repeated until the actual output matches the expected output to within acceptable tolerance. Such off-line testing is performed at the manufacturing site and is time consuming. For example, 256 (2.sup.8) different codes must be checked for an eight-bit word output converter. It also requires a very accurate voltage source for the externally applied analog input signal. In production testing, where probe application is common, ensuring accuracy of the applied calibration voltage is not easy. You may get an accurate source, but you may have a lot of noise on it. Since analog voltages to be converted are typically divided up into 256 (2.sup.8) digital levels, if a 5-volt reference V.sub.REF is used, the differences in applied testing voltage levels can be as small as 20 mV. These voltage levels can be easily swamped by noise. Therefore, it is desirable to have an ADC which does not need to use precision external signal sources for testing of its components.
In the past, ADCs have been manufactured as discrete, stand-alone chips because they are very precise elements and need to be isolated from "noise" (interfering) producing circuits, like digital microprocessors. If the ADC is a stand-alone device, some testing is already done which is reasonably quick and it may not be worthwhile to do any additional testing. In order to achieve higher densities and reduced cost, however, it is desirable to achieve an ADC which can be integrated onto a single chip with a noisy circuit, such as a microprocessor. However, once it is integrated with the microprocessor, conventional quick testing for the ADC can no longer be done. If an exhaustive test or a dynamic test including a signal-to-noise (SNR) test is to be done on an eight-bit ADC, then the test may consist of some 10,000 conversions.
Prior art built-in self-testing capabilities for ADCs test only the digital parts of the ADC, with digital test strategies being limited to things such as read/write capability of registers on the data bus and/or a scan path for other latches. An example of an integrated circuit including an ADC with this type of built-in self-testing logic is the TLC 1540 component manufactured by Texas Instruments Incorporated. However, the built-in self-testing logic on this chip leaves the analog parts of the converter (the comparator and capacitor array) untested, so if there are faults in this section, they aren't discovered until essentially the whole chip is assembled.
There is, thus, a need for a simple test which gives a high degree of confidence that at least all the analog parts of the ADOC are functioning properly prior to final assembly.
Accordingly, it is an object of the present invention to provide a method and apparatus for quickly testing the analog components of an ADC which is completely integrated onto a single chip with other components, without requiring the use of external calibrating voltages.
Another object of the present invention is to provide a self-testing circuit for an ADC which is completely self-contained and on the same chip with the ADC.
A further object of the present invention is to provide for the diagnostic testing of a successive approximation ADC with no requirement for use of precision external analog voltage sources.
Another object of the present invention is to provide for a quick self-test of a successive approximation ADC which tests the analog components of the converter while using only a digital input and output.